Expansion port for external ROM and /ROMDIS line

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6502Nerd
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Expansion port for external ROM and /ROMDIS line

Post by 6502Nerd »

Hello, hoping some experts can explain some issues which I have resolved but would like to understand why..(sorry it is a bit long, but hopefully helps to explain what I found)

I built a simple circuit on breadboard which provides for a 2nd VIA addressed at 0x380 and an EEPROM to disable the internal ROM. The 2nd VIA was for future possibilities, and the EEPROM because I have created a new ROM that hosts a new programming language which I call dflat and all low-level machine functions around I/O etc.

Everything seemed to work well, but when testing tape save/load routines, I found the CB1 line was very unstable and could not understand why. Then I also experienced strange behaviour with my new system software - very odd behaviour which made no sense. I wrote 1.0 and 1.1 Oric BASIC to the EEPROM and tried - strangely the 1.0 image seemed to work but the 1.1 image had issues with printing number (almost like just the math / fp routines or the RAM they use were corrupted).

I checked with a scope and found the lines very noisy so added some 2.2k pull-ups on the A14,A15,R/W,Phi2 lines - this seemed not to make much difference.

Anyway to cut a long story short, I first suspected the 2nd VIA so took that completely off the breadboard, but still had problems.

Then I researched some expansion board designs on the internet and found something interesting. My EEPROM is configured thus:
- My board ties /ROMDIS to ground
- I use a 74LS00 to NAND A14 and A15 to enable the /CE line of the EEPROM
- I NAND R/W and Phi2 to enable the /OE line of the EEPROM

The difference with the design on the internet is that instead of /ROMDIS tied permanently low, it is wired to the second NAND as used for the /OE. I also found that there are some problems without the pull-ups, so kept this.

So now things working well; CB1 line is stable on detecting signal transitions from tape, 1.1 image works perfectly, not more odd behaviour on my new system code.

I am happy that this works, now I can concentrate on finishing the 1st stage of my project. However, I am confused about why /ROMDIS needs to be used like this - I assumed that keeping it always low would mean my EEPROM is always selected and drives the bus according to A14,A15 and R/W,Phi2..?

I am ok with the pull-ups - I know breadboards are not the best with signal quality and noise (although my other project is an entire home computer with video, sound, 2xVIAs all on breadboard). I attach a picture which may help..

I am hoping for some explanation of the logic for /ROMDIS - just so that I am better informed! :)

(Thank you for reading all this way!)
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eeprom_expansion.jpg

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kenneth
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Re: Expansion port for external ROM and /ROMDIS line

Post by kenneth »

When I used a Winbond memory for my project of Erebus, sometimes the Oric computer freezed, I rather use an Uvprom for my tests.

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Re: Expansion port for external ROM and /ROMDIS line

Post by 6502Nerd »

kenneth wrote:
Thu Oct 22, 2020 11:14 pm
When I used a Winbond memory for my project of Erebus, sometimes the Oric computer freezed, I rather use an Uvprom for my tests.
Interesting! I would like to stick with EEPROM as it's rather easier to deal with re-programming (I make lots of fixes to my code!!).

But I am seeing stable functioning since I made /ROMDIS use the same signal going to /OE rather than tied to ground, so this is still something that would be good to understand the reason why it should be done this way (and I saw from a board on the internet).

This is where I saw the approach to /ROMDIS
http://oric.signal11.org.uk/files/pub/d ... m-rev1.gif

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Re: Expansion port for external ROM and /ROMDIS line

Post by mikeb »

Ooh, that's me :)

I certainly don't think I invented that method (it likely fell in from another interface design elsewhere) and I can't think of a good reason why tying ROMDIS low wouldn't work, if you want to shove the internal ROM aside permanently. TBH, I'm not sure why I didn't just do that myself!

Finding lines noisy is probably the root cause of your ROM related problems. Breadboards can work, but introduce lots of crosstalk, so results can vary -- if you've seen Ben Eater's 6502 computer series on YouTube, he seems to get by just fine without any breadboard induced problems.

A14/A15/R~W and Phi2 all come from the 6502, are fully driven (not open collector) and shouldn't need pullups at all. Phi2 is usually a bit "round edged", and nothing like your textbook square wave, this could cause trouble with timings. Depending on what's on Phi2, you might want to buffer it as it arrives at the board, then drive other things from the copy.

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Re: Expansion port for external ROM and /ROMDIS line

Post by 6502Nerd »

Oh cool - without your circuit having a different way to connect /ROMDIS, I don't think I would have got this working!

Yes agreed, there seems to be no reason why /ROMDIS tied low would not just work - and indeed it seems to work for *most* of the time. But yes breadboards can indeed be noisy buggers, and yes Ben Eater and other videos show this very well. But as I mentioned, I have built a pretty complete homebrew computer entirely on breadboards and running at 5.36Mhz quite, I not sure why it should be so bad here. I'm using reasonable quality breadboards from the sadly defunct Maplin company..

Another thing I wonder is whether a 27C512 (120ns) is too fast? On my homebrew computer I found very fast SRAM made the board unstable..?!?

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Re: Expansion port for external ROM and /ROMDIS line

Post by mikeb »

I struggle to picture how the EPROM being "too fast" can be a bad thing -- it's not like it can deliver data *before* it was expected, treading on something else :) Too slow, yes, big problem!

There's no tricks going on here to select the ROM early, knowing it will be late showing up with the data -- unlike some of shenanigans in the Disk Interface (where a signal has to be "advanced" -- (actually a 1MHz repeating signal delayed by 1 microsecond minus ~150ns) to compensate for how slow the following chips/FDC is in reacting and getting data onto the bus! Order early for Christmas ...)

The 27C512s I use are -20 (200ns) so not quite as flash as yours!

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Re: Expansion port for external ROM and /ROMDIS line

Post by 6502Nerd »

These EEPROMS were just what I could find on eBay - I also have 45ns device I use in my higher clocked homebrew computer.

The speed could possibly be an issue - modern devices have very fast rise and fall times which could disturb the bus. I think this may still be part of the problem.. might see if I can find a slower EEPROM, although it may still have the very small slew times.

All hypothetical of course - I am really not that wise regarding electronics despite having built a breadboard computer from scratch.. for now I'm happy things seem to be working..!

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Re: Expansion port for external ROM and /ROMDIS line

Post by 6502Nerd »

Hi mikeb

Well I have been kept awake by this for some days and even the weekend just gone. But after much frustration, I have found a stable and unstable configuration which I can reliably reproduce.

Firstly, I am using a Winbond 27E512-12 (120ns) part, and pin compatible with 27C512 as you would imagine.

If you recall I was having strange issues until I tied /ROMDIS to the NAND of A14 and A15, which also feeds the 27E512 /CE pin. In addition, there is the NAND of R/W and Phi2 which feeds the 27E512 /OE pin.

So far this is as per your circuit and seemed to be working find for a short while. But I started noticing glitches, normally seemed to happen once the machine was warmed up (say after around 3-4 mins) then I would start seeing screen or font corruption.

I messed around with many things including suspecting the custom keyboard routines I use which don't run off an interrupt but do hammer the keyboard matrix intensely - and the glitching reduced a lot when I added timers to hold off scanning the keyboard matrix in a tight loop. Reduced - but not completely eliminated. The odd thing is that when I tried a 1.1 ROM image - seemed to work fine.

But I checked and rechecked and could not see that it was my software causing the issue. So I rebuilt the expansion board on a different breadboard, as I suspected noise. Still no change!

I went back to suspecting timing issues with the 27E512. Noting from the datasheet that there is a small difference in timing between /CE and /OE, I decided to switch so that A14 NAND A15 feeds /OE and R/W NAND Phi2 feeds /CE. Remarkably, my custom ROM works completely stable on this board with no corruption, even with the keyboard matrix being hit in a tight loop.

On top of this, tying /ROMDIS permanently low also is fine!

To double check I was not imagining things, I tried switching the wires around and the screen and font corruption reappears as before.

So TLDR; I had to wire my /CE and /OE lines the opposite way to your board! I have a theory as to why, but have written too much already - I am just glad I can get on with the actual software side of the project which is why I needed this board in the first place!!!

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Re: Expansion port for external ROM and /ROMDIS line

Post by Godzil »

One important point, the original 6522 is NMOS and don't work well with modern signal level.

3.3V for example will not work with some of them (I got caught by that on one of my project) :
Chart-IC-Voltage-Switching-Levels-Grpah.png
The minimum is the theorical minimum, so even a chip supposed to give a High output from 2.8V to 3.3V may not be registered as a high by the 6522.

So be careful with the output (and input) voltage of the chip you try to interface with your oric

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Re: Expansion port for external ROM and /ROMDIS line

Post by 6502Nerd »

Yes indeed Godzil, this is something that needs to be taken account of. Indeed I found that I needed pull ups on the inputs to the 74LS00 logic chip to get nice 0V and 5V levels.

But the even doing this, which signal is used to drive which enable pin on the EEPROM is what is making a difference to what I see..

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Re: Expansion port for external ROM and /ROMDIS line

Post by Godzil »

And I got is fooled again. The output from the 6522 and ETL do not match.

NMOS:

Vih = +2.4 to 5V
Vil = -0.3V to 0.4V
Voh = 2.4V
Vol = 0.4V

(Vih = Input High, Vil = Input Low, Voh = Output High, Vol = Output low)

Can't find the proper transition voltage as it is not said in the datasheet.

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Re: Expansion port for external ROM and /ROMDIS line

Post by mikeb »

6502Nerd wrote:
Wed Nov 04, 2020 10:03 pm
screen and font corruption reappears as before.
Interesting experiment, well done for persisting with it!

That line alone tells me your EPROM is putting data onto the databus at the wrong time. It is treading on the ULA's use of the database in the "ph2 is low" half -- well, two thirds, of the clock cycle). This is also a symptom seen when using badly designed 8-bit "input port" designs from books that don't "get" Oric's clock usage, probably translated from another 6502 based system e.g. BBC -- and leaving out Ph2 in the logic. Leading to the ULA getting randomly stomped on/screen glitches. Been there, done that.
6502Nerd wrote:
Wed Nov 04, 2020 10:03 pm
So TLDR; I had to wire my /CE and /OE lines the opposite way to your board! I have a theory as to why, but have written too much already - I am just glad I can get on with the actual software side of the project which is why I needed this board in the first place!!!
OK, without looking at timing diagrams to work out exactly what happens when, A14 NAND A15 would only occur when the 6502 is accessing 0xC000-0xFFFF, but could potentially be there for almost the whole of the 1MHZ cycle -- the ULA doesn't care about the address on the bus when it is working internally. Also, consider that the 6502 knows nothing about the ULA, or its persistent chipping in on the second side of the clock, so it's within its rights to assert the address bus the whole time :) This means that A14 NAND A15 is *not* permission to talk!

From the EPROM point of view, you are supposed to apply the address you want, then drop CE to wake up the chip to go fetch the data (delay ... delay... found!). Dropping OE first, or at the same time, is "wrong" because it will enable the output buffer in the EPROM to drive the bus, but you've only JUST set the chip looking up. So for a period of time, your data output may be "randomCORRECT" or "lastvalueCORRECT"

This is why CE drops as soon as the address is presented, but OE only drops later when the answer is available *and* wanted by Oric.

From ORIC as a system, you can only allow the EPROM's OE to drive the databus when the 6502 is reading (which means ph2 high: 6502 active, and R/W high: It's a read!)

I'm puzzled why doing it backwards works better, and don't have an explanation -- if you do, please share! :)

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Re: Expansion port for external ROM and /ROMDIS line

Post by 6502Nerd »

I don't have an explanation either! Your circuit design is the logical way I have used in other decoding (e.g. my homebrew computer).

You're right that normal in designs CE goes low before OE, and the way I have it, OE would often go low before CE because the '02 will start putting the address on the bus before Phi2 goes high. However the EEPROM takes longer to respond to CE going low (if OE is already low) than the other way around - so that's the only reason I can think is the reason..?

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