Jasmin (2) clock buffering trick?

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mmu_man
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Jasmin (2) clock buffering trick?

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During the ORIC visu tonight we discussed the Jasmin controller and the tricks it uses on Phi2. I'm still puzzled as to how it's supposed to work…

I tried commenting the facebook post for the visu but it's not allowed it seems. Someone reverse engineered the schematics already, I'd like to get a scan of that to compare it to the one published in Theoric (which seems to miss at least one connection on the clock stuff).

The clock from the bus seems to be fed to a CD4069UB (UB= Unbuffered) with its output tied to the same input. From a purely logical view it should just short-circuit, but I suppose there's more to it, and I'd like to understand what exactly. I have some ideas but nothing sure yet. Possibly it turns the line into more of a current loop, forcing current in to limit parasites, but that's quite ugly.

There's an interesting article about the uses of the CD4069UB on Hackaday. But it doesn't cover this very odd use in the Jasmin.

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iss
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Re: Jasmin (2) clock buffering trick?

Post by iss »

jasmin.png
There should be NO connection between input and output of the 4069. ;)

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Re: Jasmin (2) clock buffering trick?

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That's what the schematics in Theoric shows, and that's what I thought it was, but someone said yesterday it wasn't the case, and I confirmed from my Jasmin2, Phi2 goes to 3 pins on the CD4069UB, something like 8, 10 and 11. So two inputs and one output.

So either:
- someone screwed up really good when routing the PCB from the schematics, and nobody noticed and they reproduced the mistake for Jasmin2, which would be really odd but not impossible, and maybe that could be one of the causes of the parasites when reading,
- it's done on purpose but I have no idea why exactly.

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Re: Jasmin (2) clock buffering trick?

Post by iss »

@mmu_man: Damn! You are right.
After desoldering of CD4069, the magic is revealed. The pins 1,2 and 3 are short connected!
For me there is NO other explanation - it's definitely BIG mistake!
(The article at Hackaday is cool but we have no "feedbacks" cases, we have simply "short connection").

Interesting is that the controller works (or almost) and the CD4069 is not burnt.

Now the important question for me is: what is the correct connection and is this the only bug? ;)
20210913_002939.jpg

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Re: Jasmin (2) clock buffering trick?

Post by mmu_man »

After looking at the Ampli-Bus which also has this, I'm convinced it's not a mistake but a design decision.
Screenshot_20210913_014117.png
That's something that should probably be asked on the eevblog forum and tried in pspice.

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Re: Jasmin (2) clock buffering trick?

Post by iss »

mmu_man wrote:
Mon Sep 13, 2021 1:31 am
After looking at the Ampli-Bus which also has this...[/attachment]
If someone is interested in AmpliBus schematic here is the whole article (with fixed bugs in the schematic :!: ):
AmpliBus-Theoric028-p39-40.jpg

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Re: Jasmin (2) clock buffering trick?

Post by iss »

And about the strange "short input-output connection" of CD4069 inverter it works! (kind of ...)

Here is F2 "as is":
20210914_000101.png
Here is F2 with connected CD4069 inverter with shorted input-output (as in the above AmpliBus schematic, which is actually the same as in Jasmin):
20210914_000019.png
...and here are both for easier compare:
20210914_000119.png
As you can see the rising edge is slightly improved but the falling edge is worse.
The idea behind using such "magic connection" is that the inverter plays the role of a current source (or current amplifier) - it's definitely interesting hardware hack but the benefit is debatable... the same effect can be achieved with a small capacitor (its value depend on the particular hardware implementation i.e. cable length, etc.)

To summarize: IMHO it's not worth using this hardware hack, there are many other better solution to improve the famous Oric F2 signal :)

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Re: Jasmin (2) clock buffering trick?

Post by mmu_man »

iss wrote:
Mon Sep 13, 2021 10:43 pm
If someone is interested in AmpliBus schematic here is the whole article (with fixed bugs in the schematic :!: ):
Actually there's still a bug, the GND symbol is tied to the Vcc line :twisted:
iss wrote:
Mon Sep 13, 2021 10:59 pm
And about the strange "short input-output connection" of CD4069 inverter it works! (kind of ...)

[…]

As you can see the rising edge is slightly improved but the falling edge is worse.
The idea behind using such "magic connection" is that the inverter plays the role of a current source (or current amplifier) - it's definitely interesting hardware hack but the benefit is debatable... the same effect can be achieved with a small capacitor (its value depend on the particular hardware implementation i.e. cable length, etc.)
That's what I thought, it fights the levels so they are further away from 0 and 5V, but yeah it's a little better on the shape, not sure how much though :)

Also, this works because it's an unbuffered chip, so the output gain is much less than a buffered one, which could probably be dangerous.
iss wrote:
Mon Sep 13, 2021 10:59 pm
To summarize: IMHO it's not worth using this hardware hack, there are many other better solution to improve the famous Oric F2 signal :)
I'll have to look that up for some other project of mine…

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