vsync frame skipping irq through hardware

This is the right place to discuss on how to implement hardware vsync, adding a VIA or AY chipset, puting multiple roms, or how to design a new flash expansion card.
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Twilighte
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vsync frame skipping irq through hardware

Post by Twilighte »

This is very technical and completely theoretical.
I am also unsure of its usefulness.

The vsync hardware hack connects the RGB sync output to the cassette input which is CB1 control line of the 6522.
CB1 can be used as the external clock to drive the Shift registers shifting.

So we could use this to frame skip a vsync :P

The number of frames skipped should be placed into the Shift Register like this..

Code: Select all

11111111 Will trigger an IRQ every Vsync frame
10101010 Will trigger an IRQ every 2 frames
10001000 Will trigger an IRQ every 4 frames
10000000 Will trigger an IRQ every 8 frames
So SR(Shift Register) is initially loaded with the value above then ACR is set to shift out under control of ext. clock (CB1) with mode 111.

On each vsync, the SR shifts the contents right by 1 bit with Bit0 falling off the end and onto CB2. So we can tell the 6522 beforehand to generate an interrupt on a CB2 transition by setting bit 3 in the IER.

We'll also need to handle when the shift register has shifted all 8 bits so we should also enable the Shift Register Interrupt bit 2 in the IER.

And in the IRQ we'll need to detect both sources, so we just read the IFR and detect bits 2 and 3.
On a bit 2 event we reload the shift register (this will also clear the IRQ) and on a Bit 3 event we should read PortB (to clear IRQ flag) and take this event as the indicator that the frame has been reached to do stuff.

Now obviously all this will upset the AY since CA2 and CB2 is used to control data sent to the Sound Chip through Port A.

So i would suggest we set CA2 permanently high since 01 is read and 11 is Register.

As i say this is completely theoretical but if people can think that it could be very useful then i'll do some proof of concept code :)
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Xeron
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Post by Xeron »

I don't think this scheme will work. If I understand correctly, the "interrupt on CB2 transition" only applies when CB2 is being used as an input (not when the VIA itself toggle the CB2 state). I could be wrong, so if someone could test this, that would be great.

Anyway, if that is the case, you would have to use a shift-in mode, which would read CB2 into the SR, and you would have no control over whether that was a 1 or 0 (i dunno whether reading the AY BDIR pin results in a 1, a 0, the current state of BDIR inside the GI, electrical noise or what), and therefore no control over the timing of the interrupts.
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