cumulus

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jdavis6809
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cumulus

Post by jdavis6809 »

hello,

Downloaded files from defence force svc

Unable to compile the two vhdl files with ise 13.2

Even after spotting and correcting 3 errors still fails to compile

1 line 32 "A: in std_logic_vector(1 downto 0);" should be "A: in std_logic_vector(15 downto 0);" in cumulus.vhdl file

2. line 62 " ;" missing in cumulus.vhdl file

3 ; line 51 ";" missing in wd1793.vhdl file

I think the error is in the cumulus.vhdl file because I created a project just for wd1793.vhdl and compiles ok

Any news on next batch or pcbs available?

Regards

john davis
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Chema
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Re: cumulus

Post by Chema »

Mmmm... I think somebody raised something about compiling the vhdl code...

Found in this thread: http://forum.defence-force.org/viewtopi ... &start=195

Metadata said he made a small change and compiled it as it is in the repository:
yes. you can't build the code as it is. There is a little error.
Change in Cumulus.VHDL:

port map(fdc_nCS, fdc_nRE, fdc_nWE, fdc_CLK, fdc_A, fdc_DALin, fdc_DALout, fdc_DRQ, fdc_IRQ, nRESET, nMWE, nMOE, MFS, MD, inMCRQ);
-- port map(fdc_nCS, fdc_nRE, fdc_nWE, fdc_CLK, fdc_A, fdc_DALin, fdc_DALout, fdc_DRQ, fdc_IRQ, nRESET, DBG2, nMWE, nMOE, MFS, MD, inMCRQ);
Not directly related to the problem you explained, but...
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iss
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Re: cumulus

Post by iss »

Here is my experience with VHDL sources.
You have to create project file and include all 3 files: Cumulus.ucf, Cumulus.VHDL, WD1793.VHDL.

Than use the corrected line 124 in Cumulus.VHDL - exactly as Chema said. Here 'DBG2' is undefined and obviously unneeded.

line 32: is OK in defence-force svn repository:

Code: Select all

 A: in std_logic_vector(15 downto 0);              -- 6502 Address Bus
I don't know how it's changed by you.

line 62 is:

Code: Select all

EA14: out std_logic
line 51 is:

Code: Select all

nMCRQ: out std_logic
Both lines are WITHOUT ';'.

I'm using ISE 14.7 (Linux and Windows) and compilation always succeeded.
It's possible that compiled code doesn't 'fit' in the chip - but this can be tweaked with some project properties.
jdavis6809
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Re: cumulus vhdl code

Post by jdavis6809 »

hello,

FDC: WD1793
port map(fdc_nCS, fdc_nRE, fdc_nWE, fdc_CLK, fdc_A, fdc_DALin, fdc_DALout, fdc_DRQ, fdc_IRQ, nRESET, DBG2, nMWE, nMOE, MFS, MD, inMCRQ);


this what I pasted from the vhdl file has 16 labels the same.


can anybody attach ise project file or vhdl files so I can try again

regards

john davis
jdavis6809
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Re: cumulus cpld

Post by jdavis6809 »

hello,

complies now I have removed DBG2

but get warning

after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'A<9>'. The input(s) are unused
after optimization. Please verify functionality via simulation.


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john davis
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iss
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Re: cumulus

Post by iss »

IMO, warnings should be just ignored.
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Re: cumulus

Post by Godzil »

IRL warning, especially in HDL languages should never been ignore, but in this case it is not important
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