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What does your scope/probe show is happening on the address bus after boot? If you have DRAM read-write issues, this will definitely die at "ERR_RAM_QUICK" (a JMP loop to itself, placed so that the addresses will cycle as described above). Thanks for the really quick reply. Sorry for not ...

I've burned both Mike's Diagnostic ROM and ISS's ROM. I got nothing when running Mikes ROM, but I got this with ISS's ROM: https://youtu.be/zQi-OPdDG4s Sounds right to me, so does that mean the CPU, VIA, and AY are ok? *** EDIT *** This is also hooked up to my Bench PSU and I can see that the Atmos ...

Here my diagnostic ROM running on Oric without RAM. The "busy tone" is bit tiny because no LM386 amplifier - the signal is directly from AY's output pins (not very good idea! :mrgreen: ). https://youtu.be/L28cXINhAck Wow, thats a seriously stripped down board! I'm going to source a couple...

TL;DR -- if you ripped out the CPU, VIA, PSG and ROM you'd still get a pattern :) You've changed the important multiplexer/inverter near the RAM, and the RAM itself. There's not much left to swap, other than the CPU, VIA and PSG, which are all soldered in :( I guess then I'll wait for the next batc...

I have a 16KB EPROM burned with the test ROM if you want to borrow it. Haven’t read all of the thread so just to say have you changed the 12Mhz Crystal? Haven't changed the crystal, but further up the thread is a capture from my scope showing the clock signal. that said I've not checked this since ...

So you think it’s still a ram issue? Does the pattern suggest the CPU might be functioning? The ram I’ve gotten was admittedly cheap stuff from China, but I’ve bought some more from hopefully a better source, a little more expensive so fingers crossed. None of the chips are getting hot. And the sign...

Hi. I've removed the 2 multiplexers and the inverter and socketed them. 3 new chips in. IMG_0238.JPEG I now get this: IMG_0234.jpg Swapped the ROM and its pretty much the same but with a bit of colour: IMG_0241.JPEG There's definitely a pattern there. I feel like im getting close. I haven't tried th...

I've tried the new ROM and new ULA

I tried all combinations:

New ROM, old ULA
old ROM, new ULA
new ROM, new ULA

No difference at all

I have some replacement multiplexers and a new inverter for IC's 8, 20, 21

is worth replacing them?

To be clear: NO it doesn't, not in the context I'm talking about. The system address bus, A0-15, is ONLY driven by the CPU. The ULA does NOT put anything onto this address bus. The ULA does multiplex the two halves of the system address bus (A0-15) into the 8 row and column addresses for the DRAM c...

By The way,

I wanted to say thanks to everyone for all the help so far. It's been brilliant and I feel like im learning loads.

Yes, ULA sets the address lines but ONLY for RAM and only during the low level of F2. @SpaceFlightOrange: It will sound like joke but ... do you have inserted the ROM chip(s)? :) If you have ROM programmer you can try mikeb's Diag ROM: http://oric.signal11.org.uk/html/diagrom.htm Attached is my ver...

Adding: Just realised, the only SOURCE on the address bus is the CPU. So If you really do have #FFFF (all address high) then the CPU is either crashed (given up asserting addresses) or never bothered starting. The bus floats high when idle. Tip: Pin 40 of the CPU -- once you've powered up, dab (bri...

First: Apologies, I meant pin 4 and 15 of the DRAM (RAS, CAS) not pin 3 (Write Enable) This is the CAS signal (can't remember but I think its IC12): CAS.jpg And this is IC18: CAS-IC18.jpg You must've found ground :) The case of the modulator is a big shiny ground. Just be aware that the PSU you are...

Mmmm I am not sure that pin 3 signal is correct. Isn't that the WRITE signal? If it is, then it goes out directly from the ULA. Maybe the ULA is not working or there is something in that track. Also the address lines should be jumping from 0s to 1s. They seem to be held high, as that pin 3. You sai...

Final Update for tonight.

This is the clock signal on pin7 of the ULA:
and this is one of the CPU address lines. They are all pretty much like this; some are flatter, but they are all up around this level.